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本文闡述了如何使用DS1841對數(shù)電位器調節(jié)APD偏置電路的輸出范圍。為了使調節(jié)過程更簡單，本文還提供了電子數(shù)據(jù)表。

APD偏置電路

DS1841可受溫度控制的非易失(NV)、I2C對數(shù)電位器包含了一個7位對數(shù)變化的電阻器。通過與升壓型DC-DC轉換器相配合，DS1841能夠調節(jié)施加在雪崩光電二極管的偏置電壓。利用三個外部電阻(RSER、RTOP和RPAR)調節(jié)輸出范圍(圖1)。

圖1. 利用DS1841和升壓型DC-DC轉換器(此處為MAX5026或MAX1523)構成的APD偏置電路

調節(jié)APD偏置電壓范圍

利用電子數(shù)據(jù)表DS1841 APD偏置電壓調節(jié)(xls)可以方便地調節(jié)APD偏置電壓。該電子數(shù)據(jù)表包含四個輸入變量：RTOP、RSER、RPAR以及VFB。輸入這些電阻值后，電子數(shù)據(jù)表即可計算出四個輸出值：VAPD (最大值)、VAPD (最小值)、STEP (最大值)和STEP (平均值)。此外還生成了兩個曲線圖：APD偏置與DAC碼關系曲線和每級電壓與DAC碼的關系曲線圖。圖2所示界面給出了四個變量以及通過輸入值而生成的圖形。表1定義了電子數(shù)據(jù)表所使用的參數(shù)。

圖2. 該電子數(shù)據(jù)表界面包含了四個數(shù)據(jù)輸入變量(見左上角)

表1. 使用DS1841調節(jié)APD偏置電壓范圍時的變量定義

VFB	The voltage present at the feedback node of the DC-DC converter.
VAPD (max)	The maximum voltage to which the APD bias can be set under worst-case conditions.
VAPD (min)	The minimum voltage to which the APD bias can be set under worst-case conditions.
STEP (max)	The maximum calculated voltage step that can occur between two adjacent DAC codes.
STEP (avg)	The average voltage step size that occurs across the full range.
VSTEP +20%	The voltage step size when the variable resistor is at the maximum of the process range (+20%).
VSTEP -20%	The voltage step size when the variable resistor is at the minimum of the process range (-20%).
VAPD +20%	The APD bias voltage when the variable resistor is at the maximum of the process range (+20%).
VAPD -20%	The APD bias voltage when the variable resistor is at the minimum of the process range (-20%).