• OMAP3503 Applications Processor:
  • OMAP? 3 Architecture
  • MPU Subsystem
    • Up to 720-MHz ARM Cortex™-A8 Core
    • NEON™ SIMD Coprocessor
  • Fully Software-Compatible With ARM9™
  • Commercial and Extended Temperature Grades
• ARM Cortex™-A8 Core
  • ARMv7 Architecture
    • Trust Zone®
    • Thumb®-2
    • MMU Enhancements
  • In-Order, Dual-Issue, Superscalar Microprocessor Core
  • NEON™ Multimedia Architecture
  • Over 2x Performance of ARMv6 SIMD
  • Supports Both Integer and Floating Point SIMD
  • Jazelle® RCT Execution Environment Architecture
  • Dynamic Branch Prediction with Branch Target Address
    Cache, Global History Buffer, and 8-Entry Return Stack
  • Embedded Trace Macrocell (ETM) Support for Non-Invasive Debug
• ARM Cortex™-A8 Memory Architecture:
  • K-Byte Instruction Cache (4-Way Set-Associative)
  • K-Byte Data Cache (4-Way Set-Associative)
  • K-Byte L2 Cache
• 112K-Byte ROM
• 64K-Byte Shared SRAM
• Endianess:
  • ARM Instructions - Little Endian
  • ARM Data – Configurable
• External Memory Interfaces:
  • SDRAM Controller (SDRC)
    • 16, 32-bit Memory Controller With 1G-Byte Total Address Space
    • Interfaces to Low-Power Double Data Rate (LPDDR) SDRAM
    • SDRAM Memory Scheduler (SMS) and Rotation Engine
  • SDRAM Controller (SDRC)
    • 16, 32-bit Memory Controller With 1G-Byte Total Address Space
    • Interfaces to Low-Power Double Data Rate (LPDDR) SDRAM
    • SDRAM Memory Scheduler (SMS) and Rotation Engine
  • General Purpose Memory Controller (GPMC)
    • 16-bit Wide Multiplexed Address/Data Bus
    • Up to 8 Chip Select Pins With 128M-Byte Address Space per Chip Select Pin
    • Glueless Interface to NOR Flash, NAND Flash (With ECC Hamming Code
      Calculation), SRAM and Pseudo-SRAM
    • Flexible Asynchronous Protocol Control for Interface to Custom Logic
      (FPGA, CPLD, ASICs, etc.)
    • Nonmultiplexed Address/Data Mode (Limited 2K-Byte Address Space)
• System Direct Memory Access (sDMA) Controller (32 Logical
  Channels With Configurable Priority)
• Camera Image Signal Processing (ISP)
  • CCD and CMOS Imager Interface
  • Memory Data Input
  • RAW Data Interface
  • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/10-Bit) Interface
  • A-Law Compression and Decompression
  • Preview Engine for Real-Time Image Processing
  • Glueless Interface to Common Video Decoders
  • Histogram Module/Auto-Exposure, Auto-White Balance, and
    Auto-Focus Engine
  • Resize Engine
    • Resize Images From 1/4x to 4x
    • Separate Horizontal/Vertical Control
• Display Subsystem
  • Parallel Digital Output
    • Up to 24-Bit RGB
    • HD Maximum Resolution
    • Supports Up to 2 LCD Panels
    • Support for Remote Frame Buffer Interface (RFBI) LCD Panels
  • 2 10-Bit Digital-to-Analog Converters (DACs) Supporting:
    • Composite NTSC/PAL Video
    • Luma/Chroma Separate Video (S-Video)
  • Rotation 90-, 180-, and 270-degrees
  • Resize Images From 1/4x to 8x
  • Color Space Converter
  • 8-bit Alpha Blending
• Serial Communication
  • 5 Multichannel Buffered Serial Ports (McBSPs)
    • 512 Byte Transmit/Receive Buffer (McBSP1/3/4/5)
    • 5K-Byte Transmit/Receive Buffer (McBSP2)
    • SIDETONE Core Support (McBSP2 and 3 Only) For Filter, Gain,
      and Mix Operations
    • Direct Interface to I2S and PCM Device and TDM Buses
    • 128 Channel Transmit/Receive Mode
  • Four Master/Slave Multichannel Serial Port Interface (McSPI) Ports
  • High-Speed/Full-Speed/Low-Speed USB OTG Subsystem (12-/8-Pin ULPI Interface)
  • High-Speed/Full-Speed/Low-Speed Multiport USB Host Subsystem
    • 12-/8-Pin ULPI Interface or 6-/4-/3-Pin Serial Interface
    • Supports Transceiverless Link Logic (TLL)
  • One HDQ/1-Wire Interface
  • Three UARTs (One with Infrared Data Association [IrDA] and
    Consumer Infrared [CIR] Modes)
  • Three Master/Slave High-Speed Inter-Integrated Circuit (I2C) Controllers
• Removable Media Interfaces:
  • Three Multimedia Card (MMC)/ Secure Digital (SD) With Secure
    Data I/O (SDIO)
• Comprehensive Power, Reset, and Clock Management
  • SmartReflex™ Technology
  • Dynamic Voltage and Frequency Scaling (DVFS)
• Test Interfaces
  • IEEE-1149.1 (JTAG) Boundary-Scan Compatible
  • Embedded Trace Macro Interface (ETM)
  • Serial Data Transport Interface (SDTI)
• 12 32-bit General Purpose Timers
• 2 32-bit Watchdog Timers
• 1 32-bit 32-kHz Sync Timer
• Up to 188 General-Purpose I/O (GPIO) Pins (Multiplexed With
  Other Device Functions)
• 65-nm CMOS Technology
• Package-On-Package (POP) Implementation for Memory Stacking
  (Not Available in CUS Package)
• Discrete Memory Interface (Not Available in CBC Package)
• Packages:⁽¹⁾
  • 515-pin s-PBGA package (CBB Suffix), .5mm Ball Pitch (Top),
    .4mm Ball Pitch (Bottom)
  • 515-pin s-PBGA package (CBC Suffix), .65mm Ball Pitch (Top),
    .5mm Ball Pitch (Bottom)
  • 423-pin s-PBGA package (CUS Suffix), .65mm Ball Pitch
• 1.8-V I/O and 3.0-V (MMC1 only),
  0.985-V to 1.35-V Adaptive Processor Core Voltage
  0.985-V to 1.35-V Adaptive Core Logic Voltage
  Note: These are default Operating
  Performance Point (OPP) voltages and could be
  optimized to lower values using SmartReflex™ AVS.
• Applications:
  • Portable Navigation Devices
  • Portable Media Player
  • Advanced Portable Consumer Electronics
  • Digital TV
  • Digital Video Camera
  • Portable Data Collection
  • Point-of-Sale Devices
  • Gaming
  • Web Tablet
  • Smart White Goods
  • Smart Home Controllers
  • Ultra Mobile Devices

⁽¹⁾ HiRel currently offers only CBC package. For CBB and CUS packages please contact TI sales.
OMAP is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.