Today’s class of high-performance FPGAs, such as the Altera? Stratix? III device, provide design engineers with a hardware platform that is capable of addressing the computational requirements needed to implement many
next-generation wireless and video algorithms. Although these devices provide dedicated hardware to implement the
basic building blocks of digital signal processing (DSP) algorithms such as multiply-accumulate (MAC), designers
still must meet the challenges of rapidly taking an algorithm from concept to implementation in the register transfer
level (RTL).
Historically, the design flow consisted of modeling the algorithm functionality in a high-level language such as C++
and then hand-coding it in RTL. This manual method of RTL creation is not only time consuming and error prone, but
often is highly sensitive to back-end routing delay problems. Catapult high-level C++ synthesis has been used to
build ASIC hardware sub-systems such as extremely complex and compute-intensive applications found in wireless,
video, and image processing. Combining Catapult’s ASIC capabilities with Altera Accelerated Libraries provides
designers with a rapid path from algorithms modeled in ANSI C++ to optimized RTL running in FPGA hardware.
Furthermore, this design flow allows designers to directly target the FPGA DSP blocks from C++, easily solving back-end timing problems using high-level synthesis constraints.