Recent developments in the simulation capabilities of high level mathematical modeling
tools have opened exciting new design flow possibilities.? System level support for bit
true modeling enables a designer to use a single environment to create floating and fixed-
point models, and to make scaling and rounding decisions early in the design process.? At
the same time, FPGA vendors have expanded commercial IP offerings to incorporate
higher level DSP functions.? Together, these technologies enable a new flow for data path
design that includes design iterations at the system level.? In the past, DSP FPGA design
required the combined efforts of a DSP engineer and a hardware engineer familiar with
HDL or schematic based design.? In this workshop we present a new method to derive an
HDL netlist for a data path directly from a system level tool.? The steps include
construction of an ideal mathematical model, investigation of implementation effects,
test-bench creation, and hardware netlist generation.? Traditional HDL design methods
are then used to complete the design implementation.? These concepts are illustrated
through examples of digital filter realizations, Discrete Wavelet Transforms (DWT), and
digital communications applications.