Asynchronous sample rate conversion is converting data from
one clock source at some sample rate to another clock source at
the same or a different sample rate. The simplest approach to an
asynchronous sample rate conversion is the use of a zero-order
hold between the two samplers shown in Figure 4. In an asynchronous
system, T2 is never equal to T1 nor is the ratio between
T2 and T1 rational. As a result, samples at fS_OUT will be repeated
or dropped producing an error in the resampling process. The
frequency domain shows the wide side lobes that result from
this error when the sampling of fS_OUT is convolved with the
attenuated images from the sin(x)/x nature of the zero-order
hold. The images at fS_IN, dc signal images, of the zero-order
hold are infinitely attenuated. Since the ratio of T2 to T1 is an
irrational number, the error resulting from the resampling at
fS_OUT can never be eliminated. However, the error can be significantly
reduced through interpolation of the input data at
fS_IN. The AD1896 is conceptually interpolated by a factor of 220.