These dual positive-edge-triggered D-type flip-flops are designed for 2-V to 5.5-V V_CC?operation.

A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

These devices are fully specified for partial-power-down applications using I_off. The I_off?circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.