The SN74ACT7805 is a 256-word × 18-bit clocked FIFO suited for buffering asynchronous data paths up to 67-MHz clock rates and 12-ns access

times. Two devices can be configured for bidirectional data buffering without additional logic. Multiple distributed V_CC and GND pins, along with Texas Instruments patented output edge control (OEC^TM) circuit, dampen simultaneous switching noise.

The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2\ is low, and IR is high. Data is read from memory on the rising edge of RDCLK when RDEN\, OE1\, and OE2\ are low and OR is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN\, OE1\, and OE2\ levels.