The TPD2S017 provides a robust system-level ESD solution for the high-speed lines interfacing low-voltage, ESD-sensitive core chipset. This device offers two stage ESD clamps in each line with 1- series resistor isolation. This architecture allows the device to generate very low clamp voltage during system level ESD strikes. Due to the series resistor component, the TPD2S017 provides a controlled filter roll-off for even greater spurious EMI suppression and signal integrity. This device offers a flow-through pin mapping for ease of board layout. The monolithic silicon technology allows matching component values, including clamp capacitance, series resistor matching, etc., between the differential signal pairs. Tight matching of the line capacitance and series resistors ensure that the differential signal distortion due to added ESD clamp remains minimal, and also allow the part to operate at high-speed differential data rate (in excess of 1.