基于FPGA 的神經(jīng)網(wǎng)絡(luò)自整定PID 控制器設(shè)計
The De ign of Neural Network Self_Tuning PlD Controller Ba ed on FPGA

摘要本文基于FPGA（現(xiàn)場可編程門陣列）技術(shù)實現(xiàn)了改進(jìn)的BP 網(wǎng)絡(luò)自整定PID 控制器的設(shè)計。首先，采用MATLAB 設(shè)計控制器，針對特定被控對象模型，在閉環(huán)控制系統(tǒng)中通過改進(jìn)的BP 網(wǎng)絡(luò)算法訓(xùn)練神經(jīng)網(wǎng)絡(luò)，獲得比較理想的系統(tǒng)輸出；依據(jù)訓(xùn)練好的網(wǎng)絡(luò)權(quán)值，在FPGA 集成開發(fā)環(huán)境下，基于VHDL（甚高速集成電路硬件描述語言）設(shè)計BP 網(wǎng)絡(luò)自整定PID 控制器，完成時序仿真測試，并在一種具體的FPGA 器件上實現(xiàn)。實驗表明，其設(shè)計過程合理，實現(xiàn)結(jié)果正確，適合于采用復(fù)雜智能控制策略并要求實時性、快速性的單片或小型控制系統(tǒng)。
關(guān)鍵詞改進(jìn)的BP 網(wǎng)絡(luò)自整定PID 控制器VHDL FPGA
Abstract In this paper，an improved BP neural network self-tuning PID controller based on FPGA（Field Programmable Data Array）is designed. At first，the controller is designed in MATLAB，the neural network is trained with the improved BP algorithm based on the given object model in the closed loop control system to take the perfect system output. Depending on the network weights，the BP neural network self-tuning PID controller based on VHDL（Very high speed integrated circuit Hardware Description Language）is designed under the FPGA integration development environment，then its timing simulation and its implementation at the FPGA device are completed. The experiment indicates that the design process is reasonable and the test result is accurate. The controller is fit to implement intelligent control strategy on the real-time basis，as well as fast and single-chip or small control system.
Keywords Improved BP neural network Self-tuning PID controller VHDL FPGA