Designing a 33MHz, 32-Bit PCI Target Using ispMACH Devices

The evolution of digital systems over the past two decades has placed new requirements on system designers.
They now need to design interfaces that are both high performance and compatible with other vendors’ systems. At
the same, time they need to meet immense time-to-market demands. The compatibility issue has been resolved by
designing systems with bus interfaces that are standards in the industry such as ISA, EISA, VESA and Micro Channel.
As performance became an ever more important factor, a new interface standard called PCI (Peripheral Component
Interconnect) was developed to meet the new requirements of today’s digital computer systems. PCI’s top
features include a well-documented standard supported by a special interest group and the performance of a
33MHz, 32-bit version of the specification reaching 132Mbytes per second at its peak transfer rate. This document
is a reference design solution for a 33MHz, 32-bit PCI target for ispMACH? devices. It is designed to provide users
with a starting point for designing a PCI target into a Lattice CPLD.
The reference design source code is available from Lattice upon the signing of a simple non-disclosure agreement.
The 33MHz, 32-bit PCI target reference design comes with a fully automated HDL test environment and RTL
source code. This gives the designer the flexibility to modify the back end interface to meet the requirements of the
interfacing system. Using the design’s fully developed test bench to verify its functionality, both new and experienced
designers will quickly be “up and running.” Although this design is not guaranteed to be fully PCI 2.2 compliant,
efforts have been made to ensure its conformity.
Design Goals and Limitations
The following goals were considered during development of this reference design:
? 33MHz PCI and back end interface clock speeds
? 32-bit PCI and back end I/O interfaces
? Support for two base address regions (I/O and memory regions)
? Single cycle and burst mode support for read and write cycles
? Implementation of all required PCI configuration registers
? Support for one interrupt signal from the back end device to the PCI bus
? Parity generation for all read cycles
? Strive for compliance with all PCI 2.2 requirements
? Implementation in the latest ispMACH devices
? Hierarchical HDL design, for simple end-user modifications
? A fully automated and self-checking HDL test bench for ease of verification