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電子發(fā)燒友網(wǎng)>電子資料下載>模擬數(shù)字>Multi-Voltage CMOS Circuit Des

Multi-Voltage CMOS Circuit Des

2009-07-22 | rar | 5 | 次下載 | 5積分

資料介紹

The scaling of semiconductor process technologies has been continuing for more than four decades. Advancements in process technologies are the fuel that has been moving the semiconductor industry. In response to growing customer demand for enhanced performance and functionality at reduced cost, a new process technology generation has been introduced by the semiconductor industry every two to three years during the past four decades [1]. Both the performance and the complexity of integrated circuits have grown dramatically since the invention of the integrated circuit in 1959. Microphotographs of the first monolithic integrated
circuit (Fairchild Semiconductor, 1959), the first microprocessor (Intel 4004, 1971), and a recent microprocessor (Intel Pentium 4, 2002) are shown in Figure 1.1.
Technology scaling reduces the delay of the circuit elements, enhancing the operating frequency of an integrated circuit (IC) [1]–[5]. The density and number of transistors on an IC are increased by scaling the feature size. By utilizing this growing number of available transistors in each new process technology, novel circuit techniques and microarchitectures can be employed, further enhancing the performance of the ICs beyond the levels made possible by simply scaling (or shrinking) a previous generation [1]–[7]. The price for these performance and functional enhancements has traditionally been increased design complexity
and power consumption. The generation, distribution, and dissipation of power are now at the forefront of current problems faced by IC designers.
Historically, circuit techniques and architectures employed during the evolution of the IC have followed two different paths. For a group of technologies, enhancing speed has been at the core of the design process. This class of ICs represents the high end of the performance spectrum. In this high end arena, increasing clock frequency and die size and the widespread use of power-hungry circuit techniques and microarchitectures (with continuously increasing levels of speculative execution often translated into an inefficient use of energy) have
increased power consumption many fold over the years [2], [3], [7]. Until recently, the removal of heat in high performance ICs was handled by inexpensive packaging solutions,passive heat sinks, and air fans. With the power dissipation of ICs rising well above 100 W, however, more expensive packaging and cooling solutions such as liquid cooling or refrigeration hardware will soon be required [2]–[10]. Issues related to power dissipation and heat removal are likely to be the primary cause of the end to the trend of continuously decreasing price to performance ratios of high performance ICs.

CMOS
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