CY7C131E/CY7C131AE/CY7C136E/CY7C136AE are high-speed， low-power CMOS 1K/2K × 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C131E/CY7C131AE/CY7C136E/ CY7C136AE can be used as a standalone dual-port static RAM. It is the solution to applications requiring shared or buffered data， such as cache memory for DSP， bit-slice， or multiprocessor designs. Each port has independent control pins; chip enable （CE）， write enable （R/W）， and output enable （OE）。 Two flags are provided on each port， BUSY and INT. The BUSY flag signals that the port is trying to access the same location， which is currently being accessed by the other port. The INT is an interrupt flag indicating that data is placed in a unique location［1］。 The BUSY and INT flags are push pull outputs. An automatic power-down feature is controlled independently on each port by the chip enable （CE） pins. The CY7C131E/CY7C131AE/CY7C136E/CY7C136AE are available in 52-pin Pb-free PLCC and 52-pin Pb-free PQFP. For a complete list of related documentation， click here.