The AD9252 is an octal， 14-bit， 50 MSPS ADC with an on-chip sample-and-hold circuit designed for low cost， low power， small size， and ease of use. Operating at a conversion rate of up to 50 MSPS， it is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock （DCO） for capturing data on the output and a frame clock （FCO） for signaling a new output byte are provided. Individual channel power-down is supported and typically consumes less than 2 mW when all channels are disabled.