An on-chip PLL allows users to provide a single ADC sampling clock; the PLL multiplies the ADC sampling clock to produce the corresponding JESD204A data rate clock. 2. The configurable JESD204A output block supports up to 1.6 Gbps per channel data rate when using a dedicated data link per ADC or 3.2 Gbps data rate when using a single shared data link for both ADCs. 3. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 250 MHz. 4. Operation from a single 1.8 V power supply. 5. Standard serial port interface （SPI） that supports various product features and functions， such as data formatting （offset binary， twos complement， or gray coding）， controlling the clock DCS， power-down， test modes， voltage reference mode， and serial output configuration.