These are exciting times for the system level designer/researcher. The world
seems to burgeon with embedded systems. Consumers demand superior electronic
products more often than ever before. Moore’s law continues to be valid
40 years after it was first stated, allowing the adventurous to design with billions
of transistors. Demanding managers require products in shorter time than
previously. All of this has led to an unending search for superior methods and
tools to design embedded systems.
Interminable appetite by consumers for portable embedded systems has
continued to churn out chips with ever growing functionality. Soaring nonrecurring
engineering costs of chips has forced designers towards large scale
chips which exhibit computation capability along with communication protocols.
These designs are expected to be flexible by being software upgradeable,
reduce time to market by being rapidly verifiable, and produced in large volumes
to reduce the cost per chip. To truly make such systems ubiquitous, it is
necessary to reduce the power consumed by such a system. These often conflicting
demands have meant that chips have to exhibit smaller footprint and
consume less power. For a long time now, the narrowing feature sizes of chips
and continuously reducing supply voltages were sufficient to satisfy the size
and power demands. Unfortunately, this trend towards smaller feature sizes
and lower supply voltages is slowing due to physical limitations. This has led
to looking at system level methods to reduce power in embedded systems.
Unlike circuit level methods to reduce power, system level methods often
allow a plethora of techniques to be applied at various levels. Often these
xvassuming that the designer has sufficient time. Some of these techniques are
at the architecture level-such as application specific processors, some are
run-time techniques-which respond to the workload by switching voltage and
frequency, some are at design time-such as compiler techniques which allow
lower power consumption of the compiled code.
Time is indeed changing the way we design systems. Reducing design time
and the size of a design team are increasingly crucial. Numerous tools and
methods are available to educated designer. Many of these are point tools,
though several tool vendors work tirelessly towards making these point tools
interoperable so that seamless design flows can be created, which are useable
by designers, increasing productivity several times. While such design flows
from the RTL level down are quite mature, the design tools and flows at the
system level are still evolving and will evolve for some time to come. Research
in this area is very much alive at this time and will be for the foreseeable future.
This book examines system level design techniques, which allow the automation
of system level designs, with a particular emphasis towards low
power. We expect researchers, graduate students and system level designers
to benefit from this book. The authors of the individual chapters are all well
known researchers in their respective fields.