DSP28335開發(fā)板資料:1.1 Features? High-Performance Static CMOS Technology Up to 150 MHz (6.67-ns Cycle Time) 1.9-V Core, 3.3-V I/O Design? High-Performance 32-Bit CPU (TMS320C28x) IEEE-754 Single-Precision Floating-PointUnit (FPU) 16 x 16 and 32 x 32 MAC Operations 16 x 16 Dual MAC Harvard Bus Architecture Fast Interrupt Response and Processing Unified Memory Programming Model Code-Efficient (in C/C++ and Assembly)Six Channel DMA Controller (for ADC, McBSP,XINTF, and SARAM)16-bit or 32-bit External Interface (XINTF) Over 2M x 16 Address Reach? On-Chip Memory F28335: 256K x 16 Flash, 34K x 16 SARAM F28334:128K x 16 Flash, 34K x 16 SARAM F28332: 64K x 16 Flash, 26K x 16 SARAM 1K x 16 OTP ROM? Boot ROM (8K x 16) With Software Boot Modes (via SCI, SPI,CAN, I2C, McBSP, XINTF, and Parallel I/O)
Standard Math Tables? Clock and System Control Dynamic PLL Ratio Changes Supported On-Chip Oscillator Watchdog Timer Module