提出一種新的WEP 協(xié)議中RC4 算法硬件設(shè)計(jì)方法，算法的KSA 和PRGA 兩個(gè)步驟共用同一硬件電路，每生成1 個(gè)KSA 狀態(tài)和每產(chǎn)生1 字節(jié)PRGA 數(shù)據(jù)流都只需要3 個(gè)時(shí)鐘周期。該方法具有設(shè)計(jì)簡單、密匙長度動(dòng)態(tài)可選、在加密/解密相同長度數(shù)據(jù)下所需的執(zhí)行時(shí)間較少的優(yōu)點(diǎn)，功能仿真結(jié)果表明了設(shè)計(jì)的正確性。
關(guān)鍵字：WEP 協(xié)議 RC4 算法 VHDL MAX+plusⅡ
Abstract:A new hardware design of RC4 algorithm in WEP is developed. In the scheme, the time to generate a KSA stage and the time to generate one byte PRGA data stream both need only three clock period. The scheme shows superior characteristics for its simple design and variable length key input, and it has fewer executing time when encrypting or decrypting equal length data. At last, result of functional simulation is given.
Keywords: WEP protocol RC4 algorithm VHDL MAX+plusⅡ