AP0100CS集成了Aptina的先進圖像處理管道（pipeline），具有令人驚嘆的視頻和低光照性能。借助用于寬動態(tài)范圍圖像再現(xiàn)（rendering）的高級局部色調(diào)映射(Advanced Local Tone Mapping, ALTM)功能，即使在非常困難的高對比度照明條件下也能夠生成高質(zhì)量的視頻。AP0100CS集成了具有高級轉(zhuǎn)換器功能的NTSC/PAL編碼器，可以提供模擬CCTV市場所需的高TV線分辨率。

這款產(chǎn)品為中國市場設(shè)計人員提供了過去無法獲取全新相機設(shè)計方案；也就是說，能夠利用高端IP相機傳感器的高分辨率、內(nèi)在的卓越低光照性能及WDR能力，移植應(yīng)用于模擬CCTV監(jiān)控領(lǐng)域。這種強大的設(shè)計靈活性將會帶來令人激動的新型監(jiān)控攝像機。

典型操作

A typical READ or WRITE sequence begins by the master generating a start condition on the bus. After the start condition, the master sends the 8-bit slave address/data direction byte. The last bit indicates whether the request is for a READ or a WRITE, where a “0” indicates a WRITE and a “1” indicates a READ. If the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus.

If the request was a WRITE, the master then transfers the 16-bit register address to which a WRITE will take place. This transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. The master will then transfer the 16-bit data, as two 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. The master stops writing by generating a (re)start or stop condition. If the request was a READ, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, just as in the write request. The master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, 8 bits at a time. The master generates an acknowledge bit after each 8- bit transfer. The data transfer is stopped when the master sends a no-acknowledge bit.

單次隨機讀

Figure1 shows the typical READ cycle of the host to the address. The first two bytes sent by the host are an internal 16-bit register address. The following 2-byte READ cycle sends the contents of the registers to host.

Figure 1: Single READ from Random Location

單次當(dāng)前位置讀取

Figure 2 shows the single READ cycle without writing the address. The internal address will use the previous address value written to the register.

Figure 2: Single Read from Current Location

從任意位置開始連接讀取

This sequence (Figure 3) starts in the same way as the single READ from random location . Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte READs until “L” bytes have been read.

Figure 3: Sequential READ, Start from Random Location

從當(dāng)前位置開始連接讀取

This sequence (Figure 4) starts in the same way as the single READ from current location (Figure 2). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte reads until “L” bytes have been read.

Figure 4: Sequential READ, Start from Current Location

對任意位置寫入

Figure 5 shows the typical WRITE cycle from the host to the AP0100CS.The first 2 bytes indicate a 16-bit address of the internal registers with most-significant byte first. The following 2 bytes indicate the 16-bit data.

Figure 5: Single WRITE to Random Location

從任意位置開始連續(xù)寫入

This sequence (Figure 6) starts in the same way as the single WRITE to random location (Figure 5). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte writes until “L” bytes have been written. The WRITE is terminated by the master generating a stop condition.

Figure 6: Sequential WRITE, Start at Random Location