這是一個(gè)能夠成功上板實(shí)現(xiàn)的灰度轉(zhuǎn)二值的 Verilog 程序設(shè)計(jì)，詳細(xì)的數(shù)據(jù)延時(shí)與信號(hào)延時(shí)如下所示：

首先是輸入 RGB 數(shù)據(jù)信號(hào)在第一個(gè)時(shí)鐘上升沿到來(lái)的時(shí)候，開(kāi)始從前級(jí)的模塊輸入到后級(jí)的模塊。 此時(shí)，乘法打一拍、加法打一拍、灰度打一拍、二值打一拍。

這樣，經(jīng)過(guò)一系列操作，直到最終的二值輸出，中間經(jīng)歷了 **4 **個(gè)時(shí)鐘的延時(shí)。因此，行場(chǎng)同步控制信號(hào)也需要 4 個(gè)時(shí)鐘的延時(shí)來(lái)和 RGB 數(shù)據(jù)同步。

RTL 代碼

module Gray_Binary(
input  wire        aclk,
input  wire        aresetn,
input  wire [23:0] rgb,
input  wire        i_h_sync,
input  wire        i_v_sync,
output reg         binary,
output reg         o_h_sync,
output reg         o_v_sync
);


reg  [15:0] multy1,multy2,multy3;
reg  [15:0] adder;
reg  [7:0]  gray;
wire [7:0]  i_r_8b;
wire [7:0]  i_g_8b;
wire [7:0]  i_b_8b;


assign i_r_8b = rgb[23:16];
assign i_g_8b = rgb[15:8];
assign i_b_8b = rgb[7:0];


reg i_h_sync_delay_1;
reg i_h_sync_delay_2;
reg i_h_sync_delay_3;
reg i_v_sync_delay_1;
reg i_v_sync_delay_2;
reg i_v_sync_delay_3;


always @(posedge aclk)begin
    multy1 <= i_r_8b * 8'd76;
    multy2 <= i_g_8b * 8'd150;
    multy3 <= i_b_8b * 8'd30;
end


always @(posedge aclk)begin
    adder <= multy1 + multy2 + multy3;
end


always @(posedge aclk)begin
    gray <= adder[15:8];
end


always @(posedge aclk)begin
    binary <= (gray< 8'd58)?1'b1:1'b0;
end


always @(posedge aclk or negedge aresetn) begin
    if(!aresetn)begin
        i_h_sync_delay_1<=0;
        i_h_sync_delay_2<=0;
        i_h_sync_delay_3<=0;
        i_v_sync_delay_1<=0;
        i_v_sync_delay_2<=0;
        i_v_sync_delay_3<=0;
    end
    else begin
        i_h_sync_delay_1 <= i_h_sync;
        i_h_sync_delay_2 <= i_h_sync_delay_1;
        i_h_sync_delay_3 <= i_h_sync_delay_2;
        o_h_sync <= i_h_sync_delay_3;

        i_v_sync_delay_1 <= i_v_sync;
        i_v_sync_delay_2 <= i_v_sync_delay_1;
        i_v_sync_delay_3 <= i_v_sync_delay_2;
        o_v_sync <= i_v_sync_delay_3;
    end
end


endmodule