Altera公司的28nm Stratix V FPGA包括增強的核架構(gòu),高達28Gbps和低功耗低BER的收發(fā)器,以及硬IP區(qū)塊陣列等. Stratix V FPGA包括四個GT, GX, GS和E系列,內(nèi)核工作電壓0.85V, 533-MHz/1066-Mbps 外接存儲器接口, Stratix V GX/GS/E 器件的接口電平為1.2V到3.3V, Stratix V GT 器件的接口電平為1.2V到2.5V, 非常適合用在專注于帶寬的應(yīng)用和協(xié)議,40G/100G或更高速率的數(shù)據(jù)應(yīng)用以及高性能高精度的DSP應(yīng)用.本文介紹了Stratix V FPGA系列主要特性,芯片框圖以及Stratix V FPGA在100Gb OTN多路收發(fā)器, 100GbE線路卡, 縱橫制和背板交換, 軍用雷, RF卡和通路卡和視頻服務(wù)器的應(yīng)用框圖以及采用兩片Stratix V FPGA的100-GbE線路卡框圖.

Altera’s 28-nm Stratix V FPGAs include innovations such as an enhanced core architecture, integrated transceivers up to 28 Gbps, and a unique array of integrated hard intellectual property (IP) blocks. With these innovations, Stratix V FPGAs deliver a new class of application-targeted devices optimized for:

■ Bandwidth-centric applications and protocols

■ Data-intensive applications for 40G/100G and beyond

■ High-performance, high-precision digital signal processing (DSP) applications Stratix V FPGAs are available in four variants (GT, GX, GS, and E), each targeted for a different set of applications. For higher volume production, you can prototype with Stratix V FPGAs and use the low-risk, low-cost path to HardCopy? V ASICs.Stratix V FPGAs deliver the industry’s most flexible transceivers with the highest bandwidth from 600 Mbps to 28 Gbps, low Bit Error Ratio (BER), and low power.

Stratix V transceivers have many enhancements to improve flexibility and robustness.

These enhancements include robust analog receive Clock and Data Recovery (CDR), advanced pre-emphasis and equalization for 12.5 Gbps backplanes. In addition, all transceivers are identical with full featured embedded PCS hard IP to simplify the design, lower the power, and save valuable core resources. Stratix V transceivers are designed to be standard compliant for a wide range of protocols and data rates, and are equipped with a variety of signal conditioning features to support backplane, optical module, and chip-to-chip applications

Stratix V FPGA主要特性：

■ Technology

● 28-nm TSMC process technology

● 0.85-V core voltage

■ Low power serial transceivers

● 28 Gbps transceivers on Stratix V GT devices

● 600 Mbps to 12.5 Gbps backplane capability

● Transmit pre-emphasis and de-emphasis

● Dynamic reconfiguration of individual channels

■ General purpose I/Os

● 1.6-Gbps LVDS

● 533-MHz/1066-Mbps external memory interface

● On-chip termination (OCT)

● 1.2-V to 3.3-V interfacing for Stratix V GX/GS/E devices

● 1.2-V to 2.5-V interfacing for Stratix V GT device

■ Embedded HardCopy Block

● PCI Express Gen1/Gen 2 complete protocol stack, ×1/×4/×8 end point and root port

■ Embedded transceiver hard IP

● Interlaken PCS

● Gigabit Ethernet (GbE) and XAUI PCS

● 10G Ethernet PCS

● Serial Rapid I/O (SRIO) PCS

● Common Public Radio Interface (CPRI) PCS

● Gigabit Passive Optical Networking (GPON) PCS

■ Power Management

● Programmable Power Technology

● Quartus? II integrated PowerPlay Power Analysis

■ High performance core fabric

● Enhanced ALM with 4 registers

● Improved routing architecture reduces congestion and improves compile times

■ Embedded memory blocks

● M20K: 20-Kbit with hard ECC

● MLAB: 640-bit

■ Variable precision DSP blocks

● Up to 500 MHz performance

● Natively support signal processing with precision ranging from 9×9 up to 54×54

● New native 27×27 multiply mode

● 64-bit accumulator and cascade for systolic FIRs

● Embedded internal coefficient memory

● Pre-adder/subtractor improves efficiency

● Increased number of outputs allows more independent multipliers

■ Fractional PLLs

● Fractional mode with third-order delta-sigma modulation

● Integer mode

● Precision clock synthesis, clock delay compensation, and zero delay buffering

■ Clock networks

● 717-MHz fabric clocking

● Global, quadrant, and peripheral clock networks

● Unused clock networks can be powered down to reduce dynamic power

■ Configuration

● Serial and parallel flash interface

● Enhanced AES design security features

● Tamper protection

■ High performance packaging

● Multiple device densities with identical package footprints enables seamless migration between different FPGA densities

● FBGA packaging with on-package decoupling capacitors

● Lead and RoHS-compliant lead-free options

■ HardCopy V migration

圖1。Stratix V GT/GX/GS FPGA芯片圖

表1。Stratix V GT/GX/GS FPGA型號


Stratix V FPGAs address the design challenges for applications in a variety of industries. Expand the sections below for details about specific applications.

Stratix V GT/GX/GS FPGA應(yīng)用：

1.100-Gb Optical Transport Network (OTN) Multiplexing Transponder

圖2.100Gb OTN多路收發(fā)器框圖

100Gb OTN多路收發(fā)器主要特性:

lMulti-standard client interfaces enabled through easy-to-use partial reconfiguration and serial transceivers with continuous data range of 600 Mbps to 12.5 Gbps

lEnhanced clocking flexibility with up to 44 independent transmit clock domains

lIntegrated electronic dispersion compensation (EDC) capability in transceivers to enable direct drive of optical modules (SFP+, SFP, QSFP, CFP)

l28-Gbps transceivers for next-generation optical interfaces

lAdvanced fPLL replacing external voltage-controlled crystal oscillators (VCXOs)

2.100 Gigabit Ethernet (GbE) Line Card

圖3.100GbE線路卡框圖

100GbE線路卡主要特性:

lHigher system integration through highest density and hard PCS blocks for 40 GbE, 100 GbE, and Interlaken

lHigh-bandwidth data-buffering with up to 1,600-Mbps external memory interfaces

lEfficient implementation of packet processing and traffic management functions

lHigher system performance while staying within your power and cost budget

3.Crossbar and Backplane Switch Fabric

圖4.縱橫制和背板交換框圖

縱橫制和背板交換主要特性:

lHighest bandwidth through 66 identical transceivers with continuous data rate from 600 Mbps to 12.5 Gbps

lBuilt-in advanced signal conditioning circuitry for direct drive of 10GBASE-KR backplanes

lFlexible support for various line-card interfaces with partial and dynamic reconfiguration

lOptimized implementation of scheduling functions through high level of integration

4.Military Radar Application

圖5.軍用雷達應(yīng)用框圖

軍用雷達主要特性:

lEfficient floating-point multiplication with up to 1,000 GFLOPS

lHigher signal processing bandwidth with up to 1,840 GMACS

lAutomatic single event upset (SEU) detection and correction

lDesign security with enhanced Advanced Encryption Standard (AES) algorithm and 256-bit volatile and non-volatile keys

lProductivity-boosting tools in Quartus^? II software, including DSP Builder Advanced Blockset and incremental compilation

5. RF Card and Channel Card

圖6.RF卡和通路卡框圖

RF卡和通路卡主要特性:

lReduced board space, power, and cost via fewer data channels and higher throughput per channel

lLower system latency and increased system performance and reliability via greater integration

lDesign differentiation using highest DSP- and memory-to-logic ratios

Higher MIMO and bandwidth density compared to competitive offering

6.Studio Video Server

圖7.視頻服務(wù)器框圖

視頻服務(wù)器主要特性:

Best-in-class serial digital interface (SDI) solution

Support for multiple CODECs through user-friendly partial reconfiguration

Optimal memory design with native 10-bit support

Efficient video processing with high multipliers-and memory-to-logic ratios

Complete solution via CODECs and 1080p video framework IP core

采用28nm FPGA的100GbE線路卡設(shè)計方案

The components of a 100-GbE line card include:

■ Optical interface—The optical interface unit can consist of multiple SFP+ or XFP modules, or it can be driven by 100G traffic via CFP or QSFP modules.

■ PHY—The PHY unit is the serializer/deserializer (SERDES) component of the line card. The PHY line rate and jitter specifications should be compliant with the optical interface.

■ MAC/PCS—The MAC/PCS unit performs the gearbox, scrambling, and encoding functions based on the protocol. In the case of 40-GbE or 100-GbE implementations, there is a multilane distribution (MLD) function as per the IEEE 802.3ba specifications. In addition, flow control as well as error handling is performed by the MAC.In some cases, the received 10G data from the MAC unit is aggregated before it is passed over to the network processing unit (NPU).

■ NPU—The key function of the NPU is to optimize the performance of packet processing in the evolving functional framework of the line card. Key functions include compression, classification/lookup, modification, and deep-packet inspection. The most common function of the NPU is to interface with a switch fabric device that performs complicated routing of the packets through the network.

■ Traffic manager—The primary function of the traffic manager is to offer a large number of high-speed queues, optimize queue depths, and use sophisticated scheduling mechanisms to meet the QoS requirements of the application. Because NPUs are not designed with QoS in mind, they require excessive processing power and software optimization before they can function as efficiently as a dedicated traffic manager.


圖8。100-GbE線路卡元件框圖

圖9。采用兩片Stratix V FPGA的100-GbE線路卡框圖

100-GbE線路卡主要特性：

Higher system integration through highest density and hard PCS blocks for 40 GbE, 100 GbE, and Interlaken

High-bandwidth data-buffering with up to 1,600-Mbps external memory interfaces

Efficient implementation of packet processing and traffic management functions

Higher system performance while staying within your power and cost budget