The annual market for wireless devices exceeds tens of billions of dollars
worldwide. As markets expand and evolve, there is an insatiable demand for
greater functionality in smaller form factor devices, seamless compatibility
with various communications standards, longer battery operating lifetimes,
and, of course, lower costs. The confluence of these objectives has motivated
worldwide research on system-on-chip (SOC) or system-in-package (SIP)
solutions wherein the number of off-chip components is relentlessly driven
towards zero. These objectives have in turn motivated the development of
CMOS and BiCMOS technologies that are effective in implementing digital,
analog, radio frequency, and micro-electro-mechanical functions together in
SOC solutions.
In the arena of RF integrated circuit design, efforts are aimed at the
realization of true single-chip radios with few, if any, off-chip components.
Ironically, the on-chip passive components required for RF integration pose
more serious challenges to SOC integration than the active CMOS and BJT
devices. Perhaps this is not surprising since modern digital IC designs are
dominated as much, or more, by interconnect characteristics than by active
device properties. In any event, the co-integration of active and passive
devices in RFIC design represents a serious design problem and an even
more daunting manufacturing challenge. If conventional mixed-signal design
techniques are employed, parasitics associated with passive elements
(resistors, capacitors, inductors, transformers, pads, etc.) and the package
effectively de-tune RF circuits rendering them sub-optimal or virtually
useless.