可編程邏輯芯片特別是FPGA的快速發(fā)展，使得新的芯片能夠根據(jù)具體應用動態(tài)地調(diào)整結(jié)構(gòu)以獲得更好的性能，這類芯片稱為動態(tài)可重構(gòu)FPGA芯片（DRFPGA）。然而，使用這類芯片構(gòu)建的可重構(gòu)系統(tǒng)在實際應用前還有許多問題需要解決。本文提出一個基于劃分和時延驅(qū)動的在線布局算法，來解決動態(tài)可重構(gòu)FPGA芯片的布局問題。實驗結(jié)果表明，我們的布局算法與傳統(tǒng)的布局算法相比，在時延上平均減少27%，在線長上平均減少34%，在運行時間上平均減少42%。
關(guān)鍵詞 劃分布局；時延驅(qū)動；動態(tài)可重構(gòu)FPGA；模型

Abstract The advances in the programmable logic devices especially Field-Programmable Gate Arrays (FPGA) have led to new architectures where the hardware can be dynamically adapted to the application to gain better performance. This kind of FPGA is called Dynamically Reconfigurable FPGA (DRFPGA). However, there are still many challenging problems to be solved before any practical reconfigurable system is built. In this paper, we present a partitioning-based timing-driven online placement for DRFPGAs. Experimental results show that our placement scheme achieves on average a total decrease of 27% in delay, 34% in wire-length and 42% in runtime, compared with the traditional placement methods.
Key words Partitioning-based Placement; Timing-driven; Dynamic Reconfigurable FPGA; Model