Introduction This lab guides you through the process of using Vivado IDE to create a simple HDL design targeting the Zynq device. You will simulate， synthesize， and implement the design with default settings. Finally， you will generate the bitstream and download it in to the hardware to verify the design functionality Objectives After completing this lab， you will be able to： ? Create a Vivado project sourcing HDL model（s） and targeting a specific FPGA device located on the ZedBoard or Zybo ? Use the provided Xilinx Design Constraint （XDC） file to constrain the pin locations ? Simulate the design using the Vivado simulator ? Synthesize and implement the design ? Generate the bitstream ? Configure the FPGA using the generated bitstream and verify the functionality Procedure This lab is broken into steps that consist of general overview statements providing information on the detailed instructions that follow. Follow these detailed instructions to progress through the lab1. Design Description The design consists of some inputs directly connected to the corresponding output LEDs. Other inputs are logically operated on before the results are output on the remaining LEDs as shown in Figure 1.