本文主要用來隨意記錄一下最近在為手頭的FPGA項目做約束文件時候遇到的一點關(guān)于FPGA專用時鐘管腳相關(guān)的內(nèi)容，意在梳理思路、保存學(xué)習(xí)結(jié)果、以供自己日后以及他人參考。

起因是在做約束文件中的時序例外約束部分的內(nèi)容的時候，發(fā)現(xiàn)很多單位之前的FPGA項目中的約束文件里經(jīng)常出現(xiàn)的一句時序例外約束是：

約束的對象往往是除了sys_clk之外的、由外部引入作為一些通信接口比如SPI或者MDIO接口的時鐘管腳的IBUF線。

如果不加這個約束，執(zhí)行implement的時候往往就會報error或者critical warning、內(nèi)容中也會提到加上這個約束的話、就會將嚴(yán)重警告或者錯誤降級為普通warning，但是一直沒搞明白這到底是怎么回事，所以這兩天翻閱文檔和論壇，算是弄清了個大概。

原來FPGA的管腳上有一類專用的時鐘管腳、他們一般用于將外部的時鐘信號引入FPGA、并在FPGA module中使用這些引入的時鐘信號。但是如果設(shè)計時管腳分配沒做好、或者管腳不夠用了，那么就有可能將本該接入專用時鐘管腳(或者叫做全局時鐘管腳)的信號，接到了普通IO口上，這樣只能通過添加CLOCK_DEDICETED_ROUTE FLASE繞過PAR的檢查，但是沒有解決根本問題。

在日常接觸較多的Xilinx 7系列FPGA芯片上，Xilinx論壇上的工作人員對于這一點是這樣解釋的：

If you are bringing the the clock onto the device then you need to use the CCIO (Clock capable inputs) . Every 7 series FPGA has four clock-capable inputs in each bank. Two of the four are Multi-Region Clock Capable (MRCC) and the other two are Single Region Clock Capable (SRCC). These inputs are regular I/O pins with dedicated connections to internal clock resources.

也就是說，必須使用片上的MRCC或者SRCC引腳來把外部時鐘信號引入FPGA、然后再在FPGA上使用這些引入的時鐘。

對于這二者的含義和前后級連接，在UG472的table1-1中有詳細(xì)說明：

關(guān)于這二者的區(qū)別，在xilinx forum的https://forums.xilinx.com/t5/Embedded-Processor-System-Design/MRCC-or-SRCC/m-p/787546

的下面的回答中進行了詳細(xì)說明：

The clock capable pins in a 7 series FPGA serve two purposes; access to the local clocking resources and access to the global clocking resources.

If you are using the global clocking resources (BUFG, BUFH, MMCM, PLL) then the MRCC and SRCC have exactly the same capability - there is no difference between the two.

If you are using the local clocking resources (BUFR and BUFIO), then then the SRCC and MRCC can both only drive only the BUFIO and BUFR located in the same clock region. The BUFIO can then only drive the IOB flip-flops and high speed clock of the ISERDES in the same I/O bank and the BUFR can clock all the logic (except the high speed clock of the ISERDES) in the same clock region.

The only difference between the SRCC and MRCC is that the MRCC can also drive the BUFMR. The BUFMR can then drive the BUFIO/BUFR in the same clock region as well as in the clock regions above and below the MRCC. This would generally be used for "ChipSync" (source synchronous) interfaces that need to use more pins than are available in one I/O bank.

另外在https://forums.xilinx.com/t5/Other-FPGA-Architectures/LVDS-CLK-P-N-be-routed-to-MRCC-SRCC-or-regular-differential-IOs/m-p/913220下的回答中也提到了：

MRCCs can access multiple clock regions and the global clock tree. MRCCs function the same as SRCCs and can additionally drive multi-clock region buffers (BUFMR) to access up to three clock regions.

另外作者還提到了：

if you are forwarding clock out from the device, then you can use any regular IOs,? I.e

Clock path is

Clock you want to forward -> ODDR -> OBUFDS ->Routed to any regular differential pair .

這里也就是說，如果需要將外部時鐘引入FPGA、但是不會在FPGA的module內(nèi)部將該信號作為時鐘去使用、而只是將這個引入的時鐘做一個relay或者說forward，那么就不需要將其接到MRCC/SRCC管腳（雖然這兩類管腳在一般情況下、不做時鐘引入的管腳的時候、也可以作為普通IO來使用）、而只用接到任何一個普通的IO即可。

這里還注意到的是、如果做時鐘中繼、使用的方案是選用ODDR-OBUFDS，這二者在UG471文檔中有說明。

UG471-P128：

Clock Forwarding
Output DDR can forward a copy of the clock to the output. This is useful for propagating
a clock and DDR data with identical delays, and for multiple clock generation, where every
clock load has a unique clock driver. This is accomplished by tying the D1 input of the
ODDR primitive High, and the D2 input Low. Xilinx recommends using this scheme to
forward clocks from the FPGA logic to the output pins.

此外，在UG472的table2-1中，對不同應(yīng)用場合下、時鐘輸入之后的各類BUF的連接方式進行了說明，包括各種常見的clk buffer：

clock management tiles (CMT)

Global clock buffers (BUFGCTRL, simplified as BUFG throughout this user guide).BUFGs do not belong to a clock region and can reach any clocking point on the device.?

horizontal clock buffer (BUFH/BUFHCE)?

clock enable circuit (BUFHCE)?

I/O clock buffer (BUFIO)?

regional clock buffer (BUFR)?

multi-clock region buffers (BUFMR)

另外在https://www.eefocus.com/liu1teng/blog/12-02/237897_4533d.html中的博文中提到了：輸入輸出的隨路時鐘，如果硬件上接到了普通IO上，這就有點悲劇了，盡管可以用BUFG接進全局時鐘網(wǎng)，但是，從PAD到BUFG的輸出有10ns的固有延時。這10ns無法消除，所以如果時鐘頻率超過20M左右時，skew會比較大。

這篇博文是2012年的，距離現(xiàn)在已經(jīng)略久遠(yuǎn)，所以關(guān)于BUFG的延時數(shù)據(jù)、在現(xiàn)在看起來有點不可思議、直覺上覺得太大了點、盡管作者的這個10ns的數(shù)據(jù)包含了從pad-IBUFG（可能是IBUFG，也可能是其他）-BUFG的整個延時。查閱現(xiàn)在使用的xilinx 7 系列FPGA芯片的ds181手冊、在Clock Buffers and Networks一小節(jié)的內(nèi)容中找到了BUFG的delay，如下圖所示：

根據(jù)不同速度等級的芯片、這個延時不盡相同、大概在0.1ns左右。這里的Tbccko_o對應(yīng)的就是UG472-Figure2-6中的BUFG的輸入輸出延時、如下圖所示：

另外博文中還提到：

一些處理辦法：用兩個DCM級聯(lián)來調(diào)相BUFG+DCM+DCM。

對應(yīng)現(xiàn)在使用的7series FPGA中、也就是時鐘BUFG+MMCM來實現(xiàn)時鐘的相位調(diào)整。

關(guān)于DCM，MMCM和PLL的發(fā)展歷史和區(qū)別，除了參閱UG472之外、在xilinx forum的回答下https://forums.xilinx.com/t5/Welcome-Join/DCM-MMCM-and-PLL/m-p/654372有詳細(xì)說明：

The DCM is a Digital Clock Manager - at its heart it is a Delay Locked Loop. This has the ability to deskew a clock, generate different phases of the clock, dynamically change the phase of a clock, generate related (2x) clocks, do clock division, and even generate clocks with harmonic relationships to the incoming clock. It was the only clock management block that existed in older technologies (up to Spartan-3 and Virtex-4).

In Virtex-5 and Spartan-6 the Phase Locked Loop (PLL) was introduced along with the DCM. The PLL is an analog clock management cell that can do almost everything the DCM can do with the exception of dynamic and fine phase shifting. However, it can do more precise frequency generation and can generate multiple different frequencies at the same time. It also has significantly better jitter performance than the DCM - particularly when doing frequency synthesis with large multipliers/dividers.

In Virtex-6 the MMCM - Mixed Mode Clock Manager - was introduced. This is a PLL with some small part of a DCM tacked on to do fine phase shifting (that's why its mixed mode - the PLL is analog, but the phase shift is digital). Thus the MMCM can do everything the PLL can do plus the phase shifting from the DCM. The V6 only had MMCMs.

In the 7 series, they have a combination of PLLs and MMCMs. Mostly this is so that there are more cells available for use (the PLLs are smaller, so they take less room on the FPGA die). Furthermore the PLLs are tightly bound to the I/O structures that are used for DDRx-SDRAM memory controllers (via the MIG).

As for the number of them, that is determined by the size of the device. Look at the Product Table for the device you are using - it will tell you what is in the CMT (Clock Management Tile) and how many of them are available in your device.

編輯：黃飛

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